1. Technical Field
This disclosure relates to processor memory repairs and, more particularly, to maintaining memory repairs across power state transitions.
2. Description of the Related Art
In an effort to provide more robust integrated circuits, manufacturers have implemented many testing techniques to ensure that quality devices are shipped to customers. For example, extensive device testing is usually performed before devices are shipped. If errors such as memory failures are found during manufacturing, fuses may be blown to repair these memory failures before the devices are shipped. Nevertheless some devices may develop field failures despite the best manufacturing practices. For example, some devices may experience latent memory or other logic failures that may cause catastrophic failures if theses failures are not caught. Accordingly, many devices include built-in self-test (BIST) units to test devices internally each time a device is powered up. In addition, some devices such as processors and memory devices may include self-repair units that may dynamically repair memory errors that are found by the BIST units.
Many new computing platforms include advanced power management features which include many different processor power states. More particularly, in multi-core processors there are core power states such as CC0 through CC6. Generally speaking, the higher the number, the less power the core consumes. For example, in a deep power-down state such as the CC6 power state, a core may have the supply voltage removed, or the system clock may be stopped. However, in such systems, if the power is removed, the dynamic repairs made to the memory locations may be lost, and re-running the BIST unit may not be acceptable in many cases due to the time it takes to run BIST when coming out of these deep power-down states.